This disclosure relates generally to semiconductor manufacturing, and more particularly to bonding pads on a semiconductor apparatus.
Signals on a chip in a semiconductor apparatus enter and leave by way of bonding pads, which are connected to a given device by connectors located on an edge of the device. The placement and connection of these bonding pads raise a number of issues.
In a linear approach, the devices are placed side by side, abutting each other. The devices are positioned so that the connector on the edge of each device faces the outer edge of the chip. The bonding pads are lined up in an area between the outer edges of the devices and the outer edge of the chip, and each bonding pad is connected to a device. This approach is undesirable because the area between the outer edges of the devices and the outer edge of the chip must be dedicated to bonding pad placement, and the number of bonding pads that can be placed in such configuration is limited.
One alternative is a staggered approach, where the devices are again placed side by side, abutting each other, with the devices positioned so that the connector on the edge of each device faces the outer edge of the chip. The device width is made smaller than in the linear approach, allowing the bonding pads to be staggered, creating an area between the outer edges of the devices and the outer edge of the chip where there exists a first row of bonding pads and a second row of bonding pads, each connected to a device. This approach allows more bonding pads to be used. However, even more area between the outer edges of the devices and the outer edge of the chip is dedicated to bonding pad placement compared to the linear approach. Further, the connections of the connectors to the bonding pads differs depending on which row a bonding pad is located in. The first row, closest to the devices and their connectors, has a short and strong connection path. The second row, farther away from the devices and their connectors, has a longer connections path that is weaker, which can result in signal deterioration.
Another alternative is a Circuit Under Pad (CUP) approach, where the devices are again placed side by side, abutting each other, with the devices positioned so that the connector on the edge of each device faces the outer edge of the chip. The bonding pads are then placed above the device, allowing the device edge to extend to the outer edge of the chip. This results in no lost area on the chip that must dedicated to bonding pad placement. However, in order to allow placement of a maximum number of bonding pads, the device width is again made smaller than in the linear approach, allowing the bonding pads to be staggered in their placement above the devices. This results in a first row of bonding pads and a second row of bonding pads, each connected to the device. Once again, the connections of the connectors to the bonding pads differs depending on which row a bonding pad is located in. The first row, closest to the connectors on the devices, has a short and strong connection path. The second row, farther away from the connectors on the devices, has a longer connection path that is weaker, which can result in signal deterioration if there is no increase in the number of metal layers. This also requires dedicating some of the device metal routing for the bonding pads as well as the connections.
Accordingly, it would be desirable to provide an improved method for placement and connection of bonding pads absent the disadvantages found in the prior methods discussed above.